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The present invention relates to output drivers, and in particular to multiple output drivers connected together in a telecommunication system when power to one output driver is down.
FIG. 1 illustrates output drivers (input/output drivers) in a first semiconductor chip 12 and second semiconductor chip 14. Alternately, the drivers can be on the same chip using different VDDs. Chip 12 includes a PMOS transistor 16 and an NMOS transistor 18 connected to an output line 20. PMOS transistor 16 is connected to the positive output (INP1) of a signal while NMOS transistor 18 is connected to a negative output (INN1).
Similarly, chip 14 includes a PMOS transistor 22 and an NMOS transistor 24 for driving output line 26. In one configuration, output lines 20 and 26 are connected together to provide a common output line 28.
A problem of signal amplitude deterioration arises when the power supply of either output driver fails and is off. In such a situation, when chip 14 drives output line 28 to a high state, a high voltage is also applied to output line 20 of chip 12. This will forward bias the P+/n-well diode of PMOS transistor 16 if the power supply VD1 is low. This affects the signal amplitude that chip 14 can drive to output line 28.
The present invention provides a circuit for putting an output driver into a high impedance state upon failure of the power supply. This is accomplished by providing a first transistor that is connected between the power supply and the n-well to charge the n-well potential of all the PMOS devices up to VDD. Upon failure of the supply voltage, a number of transistors are connected to couple the charged-up n-well and a gate of the PMOS drive transistor to the output line, so that they track the voltage level of the output, thereby preventing forward biasing of the P+/n-well diode.
In one embodiment, the transistors include a transistor for connecting the n-well to the output line, the transistor being activated by a low power supply voltage. A switch (NMOS) transistor is provided to isolate the gate of the PMOS drive transistor from its input signal upon a low power supply. An additional two (PMOS) transistors, both activated by a low power supply, are used to couple the gates of the PMOS drive transistor and the transfer gate transistor to the output line, so that they track the voltage levels of the output line.
For a further understanding of the nature and advantages of the invention, reference should be made to the following description taken in conjunction with the accompanying drawings.